As advanced CMOS technology continues to scale and move into the deep-sub-micron geometry dimensions for core devices, proper channel engineering of the CMOS devices becomes increasingly important. One of the more promising methods for extending the performance of CMOS devices as technology continues to scale, is the incorporation of super steep retrograde wells and a thin intrinsic region for the channel of the CMOS devices. In forming a retrograde well the dopant concentration in regions further from the gate dielectric of the transistor is higher that that in regions adjacent to the transistor gate dielectric.
A typical MOS transistor is shown in FIG. 1. Isolation structures 20 are formed in the substrate 10. The gate dielectric layer 50, the conductive gate layer 60, and the sidewall structures 70 comprise the gate stack. In an enhancement mode transistor, the source and drain regions 80 are of an opposite conductivity type to that of the substrate region 10. As described above, in a retrograde well the dopant concentration in region 30 is greater than that of the channel region 40, with a concentration gradient that is typically limited by diffusion of the dopant species. In the ideal case what is required is a super steep dopant concentration profile from region 30 to region 40 with region 40 being intrinsically doped. The use of super steep retrograde wells with intrinsically doped channel regions has significant performance advantages for CMOS devices. These advantages include reduction of short channel effects, increased mobility in the channel region, higher mobility, less parasitic capacitance, and a reduction in short channel effects. Although the super steep retrograde wells have significant advantages for advanced CMOS devices, it is very difficult to achieve these structures when manufacturing these devices for high volume integrated circuit applications. This difficulty is due to the out-diffusion of the retrograde well dopant species into the channel region especially for p-well device such as the NMOS transistor. In fact, it has been shown that current silicon processing techniques will not be able to achieve stringent doping profiles that are targeted to change by as much as three orders of magnitude in less then 4 nm by the year 2008. There is therefore a great need for new processing techniques that will allow the formation of super steep retrograde well structures with near intrinsic transistor channel regions.